Digital signal processing Question Paper - Jun 17 - Electronics Engineering (Semester 7)

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Digital signal processing - Jun 17

Electronics Engineering (Semester 7)

Total marks: 80
Total time: 3 Hours INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

Q1. Attempt any four

1.a. State and explain relation between DTFS, DFT and ZT.

(5 marks) 00

1.b. Explain the need of DSP processor.

(5 marks) 00

1.c. Differentiate between butterworth and chebyshev filter.

(5 marks) 00

1.d. Explain frequency wrapping effect in designing IIR filter.

(5 marks) 00

1.e. Compare DSP processor and microprocessor.

(5 marks) 00

2.a. Explain Gibbs phenomenon and States its configuration in FIR filter design.

(10 marks) 00

2.b. Explain different addressing mode of TMS 320C67XX DSP Processor.

(10 marks) 00

3.a. What are the salient feature of TMS 320C67XX family of DSP processor.

(10 marks) 00

3.b Compute the circular convolution of the sequence using DFT and IDFT, x1(n)={1, 2, 0} and x2(n)={2,2,1,1}.

(10 marks) 00

4.a. Compute IDFT of the following sequence using inverse FFT algorithm X(k)={3,0,3,0,3,0,3,0}

(10 marks) 00

4.b. Explain VLIW architecture in details.

(10 marks) 00

5.a. Design butterworth LPF to meet following specifications

Passband gain is 0.89

Pass band frequency edge 30Hz

Attenuation 0.20

Stopband edge 75Hz

(10 marks) 00

5.b. Design analog butterworth filter that has -2dB passband attenuation of 20 rad/sec and at least -10dB stopband attenuation at 30 rad/sec.

(10 marks) 00

Q6. Write short note on following (Any two)

6.a. Frequency transformation on IIR filters.

(10 marks) 00

6.b. Application of DSP in speech of radar processing.

(10 marks) 00

6.c. Limit cycle oscillation.

(10 marks) 00

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