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Design JFET circuit with voltage divider biasing as shown in Fig 2b with JFET parameters IDSS=12mA, VF=3.5V and ?=0. Let R1+R2=100K, IDSQ=5mA. And VDSQ=5V.
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$V_{DS}=V_{DD}-I_D(R_D+R_S)=5-(5\times10^{-3})(3+0.5)\times10^3=-12.5V$ $V_D=V_{DD}-I_DR_D$ $3.5=5-(0.005R_D)$ $R_D=\dfrac {-1.5}{-0.005}=3K\Omega$ $V_S=I_DR_S $ $V_S=6\times10^{-3}\times0.5\times10^3=3V$ $I_{R1}=I_{R2}=\dfrac {{V_{DD}}}{R_1+R_2}=\dfrac {5\times10^{-3}}{100}=50\mu A$

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