Multiplexer:-
- Multiplexer is a combinational circuit which can select one of its input and send it to output. The selection of input is based depending on the selection lines.
Multiplexer tree:-
- The multiplexer of larger size can be obtained by cascading two or more multiplexers of smaller size.
- There are two methods for cascading multiplexers. They are
- This method uses a multiplexer to combine the outputs of cascading multiplexers. This method is preferable when we want to cascade more than two multiplexers.
- This method uses a OR gate to combine the outputs of cascading multiplexers. This method is preferable when we want to cascade two multiplexers.
Truth table:-
Selection Lines |
Output |
S3 |
S2 |
S1 |
S0 |
F |
0 |
0 |
0 |
0 |
A0 |
0 |
0 |
0 |
1 |
A1 |
0 |
0 |
1 |
0 |
A2 |
0 |
0 |
1 |
1 |
A3 |
0 |
1 |
0 |
0 |
A4 |
0 |
1 |
0 |
1 |
A5 |
0 |
1 |
1 |
0 |
A6 |
0 |
1 |
1 |
1 |
A7 |
1 |
0 |
0 |
0 |
A8 |
1 |
0 |
0 |
1 |
A9 |
1 |
0 |
1 |
0 |
A10 |
1 |
0 |
1 |
1 |
A11 |
1 |
1 |
0 |
0 |
A12 |
1 |
1 |
0 |
1 |
A13 |
1 |
1 |
1 |
0 |
A14 |
1 |
1 |
1 |
1 |
A15 |
Design of 16 to 1 multiplexer using two 8 to 1 multiplexer and one 2-to-1 multiplexer:-
- The two 8:1 multiplexer and one 2:1 multiplexer are connected as shown in fig below to implement 16:1 multiplexer.
- 16:1 multiplexer requires 4 selection lines but 8:1multiplexer requires 3 selection lines and 2:1 multiplexer requires 1 selection line. The MSB in the selction lines is connected to 2: 1 multiplexer and remaining three are parallely connected to two 8:1 multiplexer.
Operation:-
- Multiplexer is a circuit which sends one of its input to output depending on the selection lines. That is when the selection lines are 0000 then its sends the input at A0 to output i.e. F. Similarly when selection lines are 1100 then its then its sends the input at A12 to output i.e. F.
- From the truth table of Multiplexer we see that when the selection lines are 0101 then its sends the input at A5 to output i.e. F. When selection lines are 0101 i.e S3=0, S2=1, S1=0 and S0=1. When the selection lines are 101 i.e.S2=1, S1=0 and S0=1 then the top multiplexer sends the input at A5 to output i.e. F1 and the bottom multiplexer sends the input at A13 to output i.e. F2. F1 & F2 are fed to the 2:1 multiplexer. As S3 is 0 it sends F1 to F i.e A5.
- From the truth table of Multiplexer we see that when the selection lines are 1111 then its sends the input at A7 to output i.e. F. When selection lines are 1111 i.e S3=1, S2=1, S1=1 and S0=1. When the selection lines are 111 i.e S2=1, S1=1 and S0=1. then the top multiplexer sends the input at A7 to output i.e. F1 and the bottom multiplexer sends the input at A15 to output i.e. F2. F1 & F2 are fed to the 2:1 multiplexer. As S3 is 1 it sends F2 to F i.e A15.
Design of 16 to 1 multiplexer using two 8 to 1 multiplexer and one OR gate:-
- The two 8:1 multiplexer and one OR gate are connected as shown in fig below to implement 16:1 multiplexer.
- 16:1 multiplexer requires 4 selection lines but 8:1multiplexer requires 3 selection lines. The complement of fourth selction line is connected to the enable input of top multiplexer and fourth selction line is directly connected to the enable input of bottom multiplexer. The outputs of both multiplexer is connected to an OR gate.