Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by microcontrollers for communicating with one or more peripheral devices over short distances. It can also be used for communication between two microcontrollers.

The SPI bus requires four bus signals namely:

1. SCLK (Serial Clock): It is also called as SCK or CLK. It works as a synchronizing signal between the transmitter and receiver.
2. MOSI (Master Out Slave In): It is also called as SIMO, SDO, DO, DOUT, SO or MTSR. This pin is used to give out the data from the transmitter or the master and taken to the receiver or the slave.
3. MISO (Master In Slave Out): It is also called as SOMI, SDI, SI or MRST. It is used to take back the data from the slave into the master to check the correctness of the data.
4. SS (Slave Select): It is also called as nCS, CS, CSB, CSN, nSS, STE or SYNC. It is used to select the slave device for a transfer of data.

The connection of the master and the slave in the SPI configuration is as shown in the figure below:

SCI

The Serial Communications Interface (SCI) module is a relatively slow, asynchronous communication port that is widely used to communicate with other embedded systems and devices. The RS-232 interface also sometimes called as the UART (Universal Asynchronous Receive and Transmit) or the SCI port.

10 bits are transmitted through TXD or received through RXD simultaneously, hence it can be said to be a 10-bit full-duplex serial communication. It consists of a start bit(0), 8-data bits(LSB first) and a stop bit(1). Baud rate is variable. Each bit is the inverse of the baud rate frequency, and each bit is maintained high or low over the interval.

Received data is obtained in the same order; reception is triggered by the falling edge of the start bit and continues if the stop bit is true (0 level) halfway through the start bit and continues if the stop bit interval. This is an anti-noise measure; if the reception circuit is triggered by noise on the transmission line, the check for a low after half a bit interval should limit false data reception.