0
Write Short notes on: i) Noise margins

Mumbai University > ELECTRO > Sem 3 > Digital Circuits and Designs

Marks: 7M

Year: Dec 2013 , Dec 2014

0
0

• The above figure shows the Input and Output profiles for Noise margins Noise is an unwanted electrical disturbance which may induce some voltage in the connecting wires used between two gates or from a gate output to load.

• Noise margin is a quantitative measure of noise immunity, where noise immunity is defined as the ability of a logic circuit to tolerate the noise without causing any unwanted changes in its output.

• In order to avoid the effects of noise, the voltage levels $V_{OH(min)}$ and $V_{IH(min)}$ are adjusted to different levels with some difference between them as shown in figure above.

• The difference between $V_{OH(min)}$ and $V_{IH(min)}$ is known as the low level noise margin $V_{NH}$. Similarly, the difference between $V_{IL(max)}$ and $V_{OL(max)}$ is known as the low level noise margin $V_{NL}$.

• When a high logic output is driving a logic circuit input, any negative noise spike greater than $V_{NH}$ can cause the voltage to drop into invalid range.

• Similarly, when a low logic output is driving a logic circuit input, any negative noise spike greater than $V_{NL}$ can cause the voltage to go into invalid range.

• Noise margin for TTL gates: $V_{NH}$ = $0.4VV_{NL}0.4V$

• Noise margin for CMOS gates: $V_{NH}$ = $1.45VV_{NL}$ = 1.45V

0