written 2.2 years ago by | modified 2.1 years ago by |
I have created a verilog code for a sequence detector that detects 1101 pattern using jk flipflop. I compiled it using modelsim se and it compiles with zero errors but during simulation it gives the following error V-sim 3033. Instantiation of "jk_ff" failed. Module file not found. I shall be very grateful if someone could help me identify the error The code is as follows:
module seq_det12(clk,rst,x,y); input clk; input rst; input x; output y; wire Ja,Jb,Ka,Kb,QA,QB,QAbar,QBbar,xbar; and m1(Ja,x,QB); xor m2(Jb,x,QA); not m3(xbar,x); or m4(Kb,xbar,QAbar); JK_ff ff1(clk,rst,Ja,QB,QA,QAbar); JK_ff ff2(clk,rst,Jb,Kb,QB,QBbar); and m5(y,x,QA,QB); endmodule
module testbench(); wire y; reg clk; reg rst; reg x; seq_det12 uut(clk,rst,x,y); initial begin $monitor($time,"x=%b y=%b",x,y); clk<=0; rst<=0;
10 x=1;
10 x=1;
10 x=0;
10 x=1;
10 x=0;
10 x=1;
10 x=1;
10 x=0;
10 x=1;
end always #5 clk=~clk; endmodule