Question: Write short notes on: Master slave JK flip flop
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Mumbai University > ELECTRO > Sem 3 > Digital Circuits and Designs

Marks: 7M

Year: May 2014

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modified 3.0 years ago  • written 3.0 years ago by gravatar for Pooja Joshi Pooja Joshi740
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  • The master slave JK flip flop is a combination of a clocked JK latch and a clocked SR latch. The clocked JK latch acts as the master and the clocked SR latch acts as the slave.

  • Master is positive level triggered and due to the presence of an inverter in the clock line, the slave is negative level edge triggered. Hence when clock=1, the master is active and slave is inactive. Vice versa happens when clock=0.

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  • The following is truth table of master slave flip flop.

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  • Operation:

Case I: When clock is not given, both master and slave are inactive and there will be no change in outputs.

Case II: For clock=1, master is active, slave inactive. As J=K=0, output of master ie Q and Q' will not change. As soon as clock goes to 0, slave becomes active, and master inactive. But since input to slave S and R is same, output of slave will also remain same.

Case III: For clock=1, master is active and slave is inactive. When J=0 and K=1, outputs of master will be Q=0, Q'=1, which will be inputs to slave. When clock=0, slave becomes active and takes inputs 0,1 to give output Q=0, Q'=1. This output will not change if clock is again made 1and then 0. Hence we get a stable output from master and slave.

Case IV: For clock=1, master is active and slave is inactive. When J=1 and K=0, outputs of master will be Q=1, Q'=0, which will be inputs to slave. When clock=0, slave becomes active and takes inputs 1,0 to give output Q=1, Q'=0. This output will not change if clock is again made 1 and then 0. Hence we get a stable output from master and slave.

Case V: When clock =1, J=K=1, master output will toggle. So S and R will invert. But slave remains inactive all this time since clock is 1. As soon as clock becomes 0, slave becomes active and master becomes inactive. So slave will also toggle. These changed outputs are returned through feedback to the master, but master does not respond to them because clock is now 0 and master is inactive. Thus, in one clock period, master and slave both toggle only once, avoiding race condition caused by multiple toggling.

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written 3.0 years ago by gravatar for Pooja Joshi Pooja Joshi740
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