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Design mod-10 synchronous counter using JK Flip Flops.Check for the lock out condition.If so,how the lock-out condition can be avoided? Draw the neat state diagram and circuit diagram with Flip Flops.

Mumbai University > COMPS > Sem 3 > Digital Logic Design and Analysis

Marks: 15 M

Year: Dec 2013

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I think J1 should be Q0.Q3'

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1) Truth Table:

enter image description here

2) K-maps:

enter image description here J0=1

enter image description here K0=1

enter image description here J1=Q0 Q3

enter image description here K1=Q0

enter image description here J2=Q0 Q1

enter image description here K2=Q0 Q1

enter image description here J3=Q0 Q1 Q2

enter image description here K3=Q0

2) Logic Circuit:

enter image description here

3) Lock out condition:

  • In the above counter the logic states 1010, 1011, 1100, 1101, 1110 and 1111 are not used. If by chance, the counter happens to find itself in any one of the unused states, its next state would not be known. It may just be possible that the counter might go from one unused state to another and never arrive at a used state. A counter whose unused states have this feature is said to suffer from LOCK OUT.
  • To avoid lock out and make sure that at the starting point the counter is in its initial state or it comes to its initial state within few clock cycles, external logic circuitry is to be provided and so we design the counter assuming the next state to be the initial state, from each unused states.
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