written 5.2 years ago by | • modified 5.2 years ago |

**Mumbai University > COMPS > Sem 3 > Digital Logic Design and Analysis**

**Marks:** 10 M

**Year:** May 2015

**1 Answer**

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Design a mod 5 synchronous up counter using J-K flip flop

written 5.2 years ago by | • modified 5.2 years ago |

**Mumbai University > COMPS > Sem 3 > Digital Logic Design and Analysis**

**Marks:** 10 M

**Year:** May 2015

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written 5.2 years ago by |

**Step 1:**

Determine the number of flip flop needed

Flip flop required are

$2^n ≥ N$

Mod 5 hence N=5

$\therefore 2^n \underline{\gt} N \\ \therefore 2^n \underline{\gt} 5 \\ N=3 \hspace{0.2cm} \text{i.e. 3 flip flop are required}$

**Step 2:**

Type of flip flop to be used: JK flip flop

**Step 3:**

**1) Excitation table for JK flip flop**

$Q_n$ | $Q_{n+1}$ | J | K |
---|---|---|---|

0 | 0 | 0 | $\times$ |

0 | 1 | 1 | $\times$ |

1 | 0 | $\times$ | 1 |

Now, we can derive excitation table for counter using above table as follows:

**2) Excitation table for counter**

**Step 4**

K-map simplification

For $J_C$

$J_c=Q_BQ_A$

For $K_C$

$K_C=1$

For $J_B$

$J_B=QA$

For $K_B$

$K_B=QA$

For $J_A$

$J_A=\overline{Q}_C$

For $K_A$

$K_A=1$

**Step 5 Logic Diagram**

**Step 6: Timing Diagram**

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