Design MOD 10 asynchronous counter

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Design MOD 10 asynchronous counter

written 7.8 years ago by

teamques10 ★ 64k

• modified 2.4 years ago

digital circuits and design

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written 7.8 years ago by

teamques10 ★ 64k

MOD 10 asynchronous counter counts from 0000 to 1001. Rest of the states are invalid. To design the combinational circuit of valid states, following truth table and K-map is drawn:

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From the above truth table, we draw the K-maps and get the expression for the MOD 10 asynchronous counter.

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Thus the above K-map shows the expression for Y which is the reset logic. This will be given to the reset inputs of the counter so that as soon as count 1010 reaches, the counter will reset. Thus the counter will count from 0000 to 1001. The implementation of the designed MOD 10 asynchronous counter is shown below:

enter image description here

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