Design mealy sequence detector to detect a sequence ----1101---- using D filpflop and logic

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Design mealy sequence detector to detect a sequence ----1101---- using D filpflop and logic

written 7.8 years ago by

teamques10 ★ 64k

• modified 2.2 years ago

digital circuits and design

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written 7.8 years ago by

teamques10 ★ 64k

A sequence detector is a sequential state machine. In a Mealy machine, output depends on the present state and the external input (x). Hence in the diagram, the output is written outside the states, along with inputs. The state diagram of a Mealy machine for a 1101 detector is:

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The state table for the above diagram:

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State assignments: Let $S_0$ = 00

$S_1$ = 01

$S_2$ = 10

$S_3$ = 11

The above state table becomes:

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Four states will require two flip flops. Consider two D flip flops. Their excitation table is shown below.
Excitation table:

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K-maps to determine inputs to D Flip flop:

enter image description here

Circuit diagram for the sequence detector:

enter image description here

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can u please tell the verilog code that can be run on xilinx software as well

7.2 years ago by teamques10 ★ 64k

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