written 7.8 years ago by
teamques10
★ 64k
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•
modified 7.8 years ago
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library IEEE;
use IEEE.std_logic_1164.all;
entity mux is
port (sel : in std_logic_vector(2 downto 0);
A,B,C,D,E,F,G,H, enable: in std_logic;
Y : out std_logic);
end mux;
architecture mux8 of mux is
begin
if (enable==0)
then
begin
process (sel, A,B,C,D,E,F,G,H)
begin
case sel is
when “000” => Y <=A;
when “001” => Y <=B;
when “010” => Y <=C;
when “011” => Y <=D;
when “100” => Y <=E;
when “101” => Y <=F;
when “110” => Y <=G;
when “111” => Y <=H;
when others => Y <=A;$
end case;
end process;
else
Y <=0;
end if;
end mux8;