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Digital Electronics and Logic Design : Question Paper Dec 2014 - Computer Engineering (Semester 3) | Pune University (PU)

## Digital Electronics and Logic Design - Dec 2014

### Computer Engg (Semester 3)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.

### Answer any one question from Q1 and Q2

1 (a) Do the following conversions:
(i) (101110.0101)2 → ( )2 (ii) (432A)16 → ( )2
(iii) (428.10)10 → ( )2
(6 marks)
1 (b) Reduce the following using K-map techniques:
f(A, B, C, D) =π (0, 2, 3, 8, 9, 12, 13, 15).
(4 marks)
1 (c) What is logic family ? Give the classification of logic family.(2 marks) 2 (a) Minimize the following expression using Quine-McClusky: f(A, B, C, D) = ∑m (0, 2, 3, 6, 7, 8, 10, 12, 13).(6 marks) 2 (b) Explain with neat diagram two input CMOS NAND gate.(6 marks)

### Answer any one question from Q3 and Q4

3 (a) Explain Look Ahead Carry generator in detail.(6 marks) 3 (b) Explain with neat diagram working of serial- n serial-out 4-bit shift register. Draw necessary timing diagram.(6 marks) 4 (a) Explain rules for BCD addition with suitable example and design one digit BCD adder using IC 7483.(6 marks) 4 (b) Design given sequence generator using J-K FF. Sequence is
1→3→5→6→7→1.
(6 marks)

### Answer any one question from Q5 and Q6

5 (a) Draw the ASM chart for the following state machine. A 2-bit up counter is to be designed with output QA QB, and enable signal 'X'. If X = 0, then counter changes the state as 00 - 01 - 10 - 11 - 00. If 'X' = 1, then counter should remain in current state. Design the circuit using JK-FF and suitable MUX.(7 marks) 5 (b) Write VHDL code for 4-bit adder using structural modelling Style.(6 marks) 6 (a) Write a VHDL code for 8 : 1 MUX using Behavioural Modelling.(7 marks) 6 (b) Draw an ASM chart, state diagram and state table for synchronous circuit having the following description.
The circuit has control input C, clock and outputs x, y, and z.
(i) If C = 1, on every clock rising edge the code on output x, y and z changes from 000 - 010 - 100 - 110 - 000 and repeats.
(ii) If C = 0, the circuit holds the present state.
(6 marks)

### Answer any one question from Q7 and Q8

7 (a) Draw and explain Basic architecture of FPGA in detail.(6 marks) 7 (b) Implement the following functions using PLA:
f1 (A, B, C) = ∑m(0, 3, 4, 7)
f2 (A, B, C) = ∑m(1, 2, 5, 7).
(7 marks)
8 (a) A combinational circuit is defined by the functions:
f1 (A, B, C) = ∑m (3, 5, 7)
f2 (A, B, C) = ∑m (4, 5, 7).
Implement the circuit with PLA having 3 input and 3 product term with 2 output.
(7 marks)
8 (b) Implement 4:1 MUX using PAL.(6 marks)