Question Paper: Digital Circuits and Design : Question Paper Dec 2015 - Electronics Engineering (Semester 3) | Mumbai University (MU)
0

## Digital Circuits and Design - Dec 2015

### Electronics Engineering (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1 (a) Explain drawback of synchronous counter.(5 marks) 1 (b) Differentiate synchronous and asynchronous counter.(5 marks) 1 (c) Draw truth table and logical diagram of half adder.(5 marks) 1 (d) Explain Fan in, Fan out, power dissipation and noise immunity with reference to digital Ics.(5 marks) 2 (a) Design MOD 12 asynchronous counter using T flip flop.(10 marks) 2 (b) Discuss Xilinx XC 9500 CPLD architecture.(10 marks) 3 (a) Design MOD-60 counter using IC 74163.(10 marks) 3 (b) Analyze the sequential state machine shown in figure. Obtain state diagram for the same. (10 marks) 4 (a) Simplify following logic function and realize using NAND gate
(i) F=1:m (1, 2, 4, 7, 10, 11, 13)+ d(9, 15)
(ii) F=2:m (1, 2, 3, 5, 8, 9, 11, 13, 15) + d(6).
(10 marks)
4 (b) Design a Mealy type sequence detector to detect a serial input sequence of 101.(10 marks) 5 (a) Draw a circuit diagram of two input TTL NAND gate and explain its operation.(10 marks) 5 (b) Design 4 bit Johnson counter using J-K Flip Flop. Explain it operation using waveform.(10 marks)

### Write a short note on.

6 (a) Fault Model.(7 marks) 6 (b) Multiplexers(7 marks) 6 (c) Noise Margin.(7 marks)

ADD COMMENTlink
 written 3.1 years ago by Team Ques10 ★ 410
Please log in to add an answer.