1) Direct Memory Access (DMA) allows devices to transfer data without subjecting the processor a heavy overhead. Otherwise, the processor would have to copy each piece of data from the source to the destination. This is typically slower than copying normal blocks of memory since access to I/O devices over a peripheral bus is generally slower than normal system RAM. During this time the processor would be unavailable for any other tasks involving processor bus access. But it can continue to work on any work which does not require bus access.
2) When large volumes of data are to be moved, a more efficient technique is required: direct memory access (DMA).
3) DMA involves an additional module on the system bus. This module is called the DMA module and it is shown in Figure 4. The DMA module is capable of mimicking the processor and indeed, of taking over control of the system from the processor. It needs to do this to transfer data to and from memory over the system bus.
4) The DMA module must use the bus only when the processor does not need it, or it must force the processor to suspend operation temporarily.
5) It is also referred to as cycle stealing, because the DMA module in effect steals a bus cycle. When the processor wishes to read or write a block of data, it issues a command to the DMA module, by sending to the DMA module the following information:
Whether a read or write is requested, using the read or write control line between the processor and the DMA module
The address of the I/O device involved, communicated on the data lines
The starting location in memory to read from or write to, communicated on the data lines and stored by the DMA module in its address register
The number of words to be read or written, again communicated via the data lines and stored in the data count register.
6) The Control Logic in the DMA module is responsible for the generation of control signals.
7) The processor then continues with other work. It has delegated this I/O operation to the DMA module. The DMA module transfers the entire block of data, one word at a time, directly to or from memory, without going through the processor. When the transfer is complete, the DMA module sends an interrupt signal to the processor.
8) Thus, the processor is involved only at the beginning and end of the transfer. In the instruction cycle the processor may be suspended. In each case, the processor is suspended just before it needs to use the bus. The DMA module then transfers one word and returns control to the processor.
9) Note that this is not an interrupt; the processor does not save a context and do something else. Rather, the processor pauses for one bus cycle. The overall effect is to cause the processor to execute more slowly. Nevertheless, for a multiple-word I/O transfer, DMA is far more efficient than interrupt-driven or programmed I/O.
10) The configuration explained above is shown in Figure5 (a), it is inexpensive but inefficient. As with processor-controlled programmed I/O, each transfer of a word consumes two bus cycles. The number of required bus cycles can be cut substantially by integrating the DMA and I/O functions, as Figure 5(b) shows. There is a path between the DMA module and one or more I/O modules that does not include the system bus.
11) The DMA logic may actually be a part of an I/O module, or it may be a separate module that controls one or more I/O modules. This concept can be taken one step further by connecting I/O modules to the DMA module using an I/O bus; this is shown in Figure 5(c). This reduces the number of I/O interfaces in the DMA module to one and provides for an easily expandable configuration.
12) In both cases Figure 5(b) and Figure5(c), the system bus that the DMA module shares with the processor and memory is used by the DMA module only to exchange data with memory. The exchange of data between the DMA and I/O modules takes place off the system bus.