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1
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5.5k
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Design Full Subtractor using PLA.
digital system design updated 4.3 years ago by teamques10 ★ 70k
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1.1k
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Design a 8 bit up counter using 74163, draw the circuit diagram & explain its working.
digital system design updated 4.0 years ago by rjran106 • 20
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578
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Write a note on Magnitude Comparator
digital system design updated 4.3 years ago by phenjoisilab • 0
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1.0k
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Analyze the clocked synchronous machine given below. Write excitation equations, transition table and state/output table. Also draw the state diagram
digital system design updated 4.3 years ago by teamques10 ★ 70k
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660
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Eliminate redundant states and draw reduced state diagram
digital system design updated 4.3 years ago by teamques10 ★ 70k
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794
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Draw the data unit for following RTL description
digital system design updated 4.3 years ago by teamques10 ★ 70k
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563
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Differentiate between signal and variable
digital system design updated 4.3 years ago by teamques10 ★ 70k
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1.1k
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Design a counter which counts the count from 3 to 12 using IC 74163.
digital system design updated 4.3 years ago by teamques10 ★ 70k
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2.7k
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Design MOD-12 Counter using IC 7493 and logic gates.
digital system design updated 4.3 years ago by teamques10 ★ 70k
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856
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Write a VHDL code for 3:8 decoder with active low output.
digital system design updated 4.3 years ago by teamques10 ★ 70k
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1.1k
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Shown below is the state table for sequential machine, using implication chart method, eliminate redundant states and obtain minimized state diagram.
digital system design updated 4.3 years ago by teamques10 ★ 70k
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1.5k
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Construct ASM chart of sequence detector which detect the sequence 1001. The output Z becomes 1 along with the last correct bit of the sequence.
digital system design updated 4.3 years ago by teamques10 ★ 70k
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2.6k
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Differentiate between IC 7490, IC 7492, IC 7493.
digital system design updated 4.3 years ago by teamques10 ★ 70k
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1.5k
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Design a MOD 61 up counter using IC 74163 and explain its working.
digital system design updated 4.3 years ago by teamques10 ★ 70k
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623
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Create VHDL code for Implementation of 4:1 MUX using two different architecture modelling styles.
digital system design updated 4.3 years ago by teamques10 ★ 70k
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861
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Write a VHDL code for state diagram given below
digital system design updated 4.3 years ago by teamques10 ★ 70k
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765
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Evaluate the value of output variable for following signal declarations.
digital system design updated 4.3 years ago by teamques10 ★ 70k
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691
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Analyse the sequential circuits shown below. Derive the excitation equation transition table and state diagram.
digital system design updated 4.3 years ago by teamques10 ★ 70k
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570
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Implement the following Boolean equations single 8:1 MUX and few logic gates:
digital system design updated 4.2 years ago by krithikkm200 • 10
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2.2k
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Using one's and two compliment methods perform (52)10-(18)10
digital logic design digital system design updated 4.3 years ago by krithikkm200 • 10
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501
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Digital system design
digital system design updated 4.4 years ago by jaspreet19120027544 • 10
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743
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Design a mod 10 synchronous down counter useing jk flipflop
digital system design updated 4.4 years ago by pointbreak7876 • 10
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479
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Mealy type sequence detector
digital system design updated 4.0 years ago by dineshkumar48g905 • 20
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439
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Moore state diagram
digital system design updated 4.0 years ago by dineshkumar48g905 • 20
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