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Admin: Abhishek Tiwari

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Abhishek Tiwari ♦♦ 30
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Posts by Abhishek Tiwari

<prev • 1,503 results • page 1 of 151 • next >
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Draw and explain floating point addition subtraction algorithm.
... **Mumbai University** > Computer Engineering > Sem 4 > Computer organization and Architecture **Marks:** 10M **Year:** Dec 2018 ...
coa(24) written 6 days ago by Abhishek Tiwari ♦♦ 30
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Write Short Notes on : Performance measures
... **Mumbai University** > Computer Engineering > Sem 4 > Computer organization and Architecture **Marks:** 10M **Year:** Dec 2018 ...
coa(24) written 6 days ago by Abhishek Tiwari ♦♦ 30
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Consider a cache memory of 16 words. Each block consists of 4 words. Size of the main memory is 256 bytes. Draw associative mapping and calculate TAG, and WORD size.
... **Mumbai University** > Computer Engineering > Sem 4 > Computer organization and Architecture **Marks:** 10M **Year:** Dec 2018 ...
coa(24) written 6 days ago by Abhishek Tiwari ♦♦ 30
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What is Microprogram? Write microprogram for following operations.
... i) ADD R1, M, Register R1 and Memory location M are added and result store at Register R1. ii) MUL R1, R2 Register R1 and Register R2 are multiplied and result store at Register R1. **Mumbai University** > Computer Engineering > Sem4 > Computer Organization and Architecture **Marks:** 10M ...
coa(24) written 6 days ago by Abhishek Tiwari ♦♦ 30
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A program having 10 instructions (without Branch and Call instructions) is executed on non-pipeline and pipeline processors.
... All instructions are of same length and having 4 pipeline stages and time required to each stage is 1nsec. i) Calculate time required to execute the program on Non-pipeline and Pipeline processor. ii) Calculate Speedup **Mumbai University** > Computer Engineering > Sem4 > Computer Organi ...
coa(24) written 6 days ago by Abhishek Tiwari ♦♦ 30
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Write short notes: Principle of locality of references
... **Mumbai University** > Computer Engineering > Sem 4 > Computer Organization **Marks:** 10M **Year:** May 2018 ...
coa(24) written 6 days ago by Abhishek Tiwari ♦♦ 30
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Answer: A: Explain the page address translation in case of virtual memory and explain TLB
... **Virtual Memory:-** 1) Virtual Memory was introduced in the system in order to increase the size the size of memory. 2) A hardware unit called Memory Management Unit (MMU) translates Virtual addresses into physical addresses. 3) If CPU wants data from main memory and it is not present in main me ...
written 7 days ago by Abhishek Tiwari ♦♦ 30
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Explain the page address translation in case of virtual memory and explain TLB
... **Mumbai University** > Computer Engineering > Sem4 > Computer Organization and Architecture **Marks:** 10M **Year:** May 18 ...
coa(24) written 7 days ago by Abhishek Tiwari ♦♦ 30
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Calculate the hit and miss using various page replacement policies LRU, OPT, FIFO for following sequence (page frame size 3) 4,7,3,0,1,7,3,8,5,4,5,3,4,7,534 state which one is best for above example?
... **Mumbai University** > Computer Engineering > Sem 4 > Computer Organization **Marks:** 10 M **Year:** Dec 2017 ...
coa(24) written 8 days ago by Abhishek Tiwari ♦♦ 30
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In Floating point representation how to identify sign of exponent?
... **Mumbai University** > Computer Engineering > Sem 4 > Computer Organization **Marks:** 5 M **Year:** Dec 2017 ...
coa(24) written 8 days ago by Abhishek Tiwari ♦♦ 30

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