nilimazade.mtech

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Posts by nilimazade.mtech

<prev • 61 results • page 1 of 7 • next >
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Find out page fault for following string using FIFU LFU LRU method.2,1,3,1,5,4,2,1,5 (Consider page frame size=3)
... **Subject:** Computer Organization **Topic:** Memory Organization **Difficulty:** High ...
co(46) written 16 months ago by nilimazade.mtech0 • updated 16 months ago by awari.swati831250
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A 32 bit processor has a 32 bit memory address. It has 8 kb of cache memory. The computer follows 4 way set associate mapping with each cache line size being 16 bytes. Show the memory address form
... **Subject:** Computer Organization **Topic:** Memory Organization **Difficulty:** High ...
co(46) written 16 months ago by nilimazade.mtech0 • updated 16 months ago by awari.swati831250
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Show the address decoding for 128 KB ROM C32 bit memory using 32 bit address
... **Subject:** Computer Organization **Topic:** Memory Organization **Difficulty:** High ...
co(46) written 16 months ago by nilimazade.mtech0 • updated 16 months ago by awari.swati831250
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Calculate the effective memory access time for M1:50 ns access time, M2:400 ns access time and hit ratio of M1:0.95
... **Subject:** Computer Organization **Topic:** Memory Organization **Difficulty:** High ...
co(46) written 16 months ago by nilimazade.mtech0 • updated 16 months ago by awari.swati831250
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Consider 4 way set associative cache mapping with cache block size = 16 bytes, cache size = 8 K, main memory size = 64K. Design cache structure and show how the processor address is interpreted
... **Subject:** Computer Organization **Topic:** Memory Organization **Difficulty:** High ...
co(46) written 16 months ago by nilimazade.mtech0 • updated 16 months ago by awari.swati831250
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Explain how virtual address is converted o physical address using paging. Also explain translation look aside buffer.
... **Subject:** Computer Organization **Topic:** Memory Organization **Difficulty:** High ...
co(46) written 16 months ago by nilimazade.mtech0 • updated 16 months ago by awari.swati831250
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Define set associative cache
... **Subject:** Computer Organization **Topic:** Memory Organization **Difficulty:** High ...
co(46) written 16 months ago by nilimazade.mtech0 • updated 16 months ago by awari.swati831250
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memory has 3 pages and the processor required pages from virtual memory in the following order.2,3,2,1,5,2,4,5,3,2,5,2.Show the implementation of FIFO,LRU.
... **Subject:** Computer Organization **Topic:** Memory Organization **Difficulty:** High ...
co(46) written 16 months ago by nilimazade.mtech0 • updated 16 months ago by awari.swati831250
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Explain chache-memory, with its mapping technique
... **Subject:** Computer Organization **Topic:** Memory Organization **Difficulty:** High ...
co(46) written 16 months ago by nilimazade.mtech0 • updated 16 months ago by awari.swati831250
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Explain page replacement algorithm. Find out page fault for following string using LRU method.6,0,12,0,30,4,2,30,32,1,20,15(Consider page frame size=3)
... **Subject:** Computer Organization **Topic:** Memory Organization **Difficulty:** High ...
co(46) written 16 months ago by nilimazade.mtech0 • updated 16 months ago by awari.swati831250

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Popular Question 16 months ago, created a question with more than 1,000 views. For Compare RISC and CISC architecture.
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Popular Question 16 months ago, created a question with more than 1,000 views. For Draw and explain IA-32 architecture
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Epic Question 16 months ago, created a question with more than 10,000 views. For Compare RISC and CISC architecture.
Great Question 16 months ago, created a question with more than 5,000 views. For Compare RISC and CISC architecture.