... **2. Low power design consideration** Static $P_{ds}=V_{DD}.I_D$ dynamic $Q=C_oV_{DD}$ $= V_{DD}.Q/t$ $=V_{DD}^2 . C_o.f$ Total average $P= V_{ ...

... **1. Clocking and system design** **1.Clock generation distribution and stabilization** *=>clock generation* - Clock signals are the heartbeats of the digital system - A simple techinque used for an chip generation of a primary clock signal would be to use a ring oscillator ![enter image des ...

... **2. array multiplier** - Multiplication basic operation in DSP multiplies occupies larger areas long latency and consume considerate power - A Multiplier circuit works on two input multipliers multiplier the product of two numbers is obtained by adding the multiple and itself the number of times ...

... **Module 5** *1. adders* a) half adder ![enter image description here][1] S= A(+)B=AB+AB C=A.B Implementation Sum S=A+B=AB+AB(XOR) Carry=A.B S=A+B = AB+AB(XNOR) C=A.B De morgan =A+B ![enter image description here][2] *b) full adder* |A|B|$C_{in}$|S|C| |-------|---------|---- ...

... **Module 4** |SRAM|DRAM| |------|------| |Retained stored info as long as power supply On. Content is lost as soon as supply is removed|loses its stored info in a few milli sec even though its power supply is on| |Uses conventional flip Flop to store bit 0 or 1|store info in the form of charge on a ...

... Resistive load ![enter image description here][1] Semiconductor memories |SRAM|DRAM| |------|------| |Retained stored info as long as power supply On. Content is lost as soon as supply is removed|loses its stored info in a few milli sec even though its power supply is on| |Uses conventional fli ...

... ![enter image description here][1] ![enter image description here][2] It memory cell (DRAM) - Write -1. Drive bit line -2. Select Rou - Read 1. precharge bit line to $V_{dd}/2$. 2. Select row 3. Cell and bit line share charges - Minute voltage change on BL 4. Sense (fancy sense amp.).Can ...

... **SRAM** ![enter image description here][1] *Semiconductor memories* ![enter image description here][2] ![enter image description here][3] Circuit topology of CMOS static as SRAM cell ![enter image description here][4] Resistive load ![enter image description here][5] Static power consumpti ...

... Memory organisation - Memory –group of letters to arrays bis - Type of memories ![enter image description here][1] It is used to increase the apparent size of the physical memory. The assumption is the address generated by the processor directly specifies physical location in the memory but the ...

... **Design Styles**: 1. Static CMOS Design: ![enter image description here][1] Q Implement 2 : 1 MUX using transmission gate. ![enter image description here][2] Q 4 : 1 MUX ![enter image description here][3] ![enter image description here][4] - Implement: $F = AB + AB^{-}C + A^{-}C$ Using tra ...