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User: awari.swati831

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Posts by awari.swati831

<prev • 1,099 results • page 1 of 110 • next >
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Answer: A: Design a VHDL Code for 4 Bit Ripple Carry Adder.
... **VHDL Code for 4 Bit Ripple Carry Adder:** library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Ripple_Adder is Port ( A : in STD_LOGIC_VECTOR (3 downto 0); B : in STD_LOGIC_VECTOR (3 downto 0); Cin : in STD_LOGIC; S : out STD_LOGIC_VECTOR (3 downto 0); Cout : out STD_LOGIC); end Ripple_Adde ...
written 21 days ago by awari.swati83190
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Answer: A: Design a VHDL Code for BCD to 7 Segment Decoder.
... **VHDL Code for BCD to 7 segment display using combinational logic:** library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity bcd_7seg is Port ( B0,B1,B2,B3 : in STD_LOGIC; A,B,C,D,E,F,G : out STD_LOGIC); end bcd_7seg; architecture Behavioral of bcd_7seg is begin A <= B0 OR B2 OR (B1 AND B ...
written 21 days ago by awari.swati83190
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Answer: A: Design a VHDL Code for 2:4 Decoders.
... **VHDL Code for 2:4 Decoders:** library IEEE; use IEEE.STD_LOGIC_1164.all; entity decoder is port( a : in STD_LOGIC_VECTOR(1 downto 0); b : out STD_LOGIC_VECTOR(3 downto 0) ); end decoder; architecture bhv of decoder is begin process(a) begin case a is when "00" => b <= "0001" ...
written 21 days ago by awari.swati83190
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Answer: A: Design a VHDL Code for 4:2 Encoders.
... **VHDL Code for 4 to 2 encoder using case statement:** library IEEE; use IEEE.STD_LOGIC_1164.all; entity encoder is port( a : in STD_LOGIC_VECTOR(3 downto 0); b : out STD_LOGIC_VECTOR(1 downto 0) ); end encoder; architecture bhv of encoder is begin process(a) begin case a is ...
written 21 days ago by awari.swati83190
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Answer: A: Design a VHDL Code for Full Subtractor.
... **VHDL Code for Full Subtractor:** library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fs1 is Port ( x : in STD_LOGIC; y : in STD_LOGIC; bin : in STD_LOGIC; d : out STD_LOGIC; bout : out STD_LOGIC); end fs1; architecture Behavi ...
written 21 days ago by awari.swati83190
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Answer: A: Design a VHDL Code for Half Subtractor.
... **VHDL Code for Half Subtractor:** library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hs1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; diff : out STD_LOGIC; borrow : out STD_LOGIC); end hs1; architecture Behavioral of hs1 is ...
written 21 days ago by awari.swati83190
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Answer: A: Design a VHDL Code for Full Adder.
... **Design a VHDL Code for Full Adder:** ENTITY full_adder IS --- Full Adder PORT(a,b,c: IN BIT ; sum, carry : OUT BIT); END full_adder; ARCHITECTURE full_adder_beh OF full_adder IS BEGIN PROCESS(a,b,c) -- Sensitive on all the three bits VARIABLE temp :BIT; B ...
written 21 days ago by awari.swati83190
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Answer: A: Design a VHDL Code for Half Adder.
... **Design a VHDL Code for Half Adder:** ENTITY half_adder IS --- Half Adder PORT(a,b:IN BIT; s,c :OUT BIT); END half_adder; ARCHITECTURE half_adder_beh OF half_adder IS BEGIN s <= a XOR b; -- Implements Sum for Half Adder c <= a AND b; -- Implemen ...
written 21 days ago by awari.swati83190
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Answer: A: Design a VHDL Code for 4 bit full adder.
... **VHDL Code for 4-bit full adder/ 4 bit Ripple Carry Adder:** library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Ripple_Adder is Port ( A : in STD_LOGIC_VECTOR (3 downto 0); B : in STD_LOGIC_VECTOR (3 downto 0); Cin : in STD_LOGIC; S : out STD_LOGIC_VECTOR (3 downto 0); Cout : out STD_LOGIC) ...
written 21 days ago by awari.swati83190
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Answer: A: Design a VHDL Code for Multiplexer & Demultiplexer.
... **VHDL Code for 4:1 Mux:** library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux_4to1 is port( A,B,C,D : in STD_LOGIC; S0,S1: in STD_LOGIC; Z: out STD_LOGIC ); end mux_4to1; architecture bhv of mux_4to1 is begin process (A,B,C,D,S0,S1) is begin if (S0 ='0' and S1 = '0') then ...
written 21 days ago by awari.swati83190

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