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User: dukare030296hemant

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Posts by dukare030296hemant

<prev • 189 results • page 1 of 19 • next >
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Answer: A: Derive Equation for o/p noise voltage of CS stage
... ![enter image description here][1] We model the thermal and flicker noise of $M_1$ by 2 current -> $\hspace{2cm}\bar{I_{n,th}^2}=4KT(\frac{2}{3})g_m$ $\hspace{2cm}\bar{I_{n,1/f}^2}=\frac{Kg_m^2}{C_{OX}WLf}$ We also represent thermal noise of $R_D$ by current sour ...
written 4 months ago by dukare030296hemant50 • updated 4 months ago by Sanket Shingote ♦♦ 220
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Answer: A: Explain High Frequency analysis of CS Stage
... ![enter image description here][1] Using Miller's theoram, $C_{GS}$ can be shifted to input and output side. Modified circuit using Miller's theoram, ![enter image description here][2] Input => Total capacitance seen from (X) to ground, $\hspace{1cm}=C_{GS}+(1-A_v)C_{GD}\hspac ...
written 4 months ago by dukare030296hemant50 • updated 4 months ago by Sanket Shingote ♦♦ 220
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Answer: A: Explain Source degeneration.
... **For MOSFET in saturation,** $\hspace{2cm}I_D=\frac{1}{2}\mu_n C_{OX}\frac{W}{L}(V_{GS}-V_{th})^2$ where, $(V_{GS}-V_{th})$ -> $I_D$ dependant on square of overdrive voltage. - In some applications, square law dependence of $I_D$ on overdrive voltage introduces excessive non-linear ...
written 4 months ago by dukare030296hemant50 • updated 4 months ago by Sanket Shingote ♦♦ 220
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Answer: A: Explain (a) Slow rate (b) CMRR (c) input range Limitations (d) Power Supply Reje
... **(a) Slew Rate:** i) Slew rate can be defined as maximum possible rate of change of op-amp output voltage. $\hspace{2cm}SR=\frac{dV_0}{dt}|_{max}\,\,\,(V/\mu sec) $ $\hspace{8cm}$, ideally SR should be infinity. ii) The slew rate imposes high frequency limitations on the device. ...
written 4 months ago by dukare030296hemant50 • updated 4 months ago by Sanket Shingote ♦♦ 220
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Answer: A: Discuss stability issues & frequency compensation of two stage operational ampli
... - 2 stage opamps are used when the output voltage swing must be maximised. - As shown in figure, we can identify 3 poles, - at X (or Y) - at E (or F) - at A (or B) - Pole X lies at relatively high frequencies. - At node A, the small signal resistance is lower ...
written 4 months ago by dukare030296hemant50 • updated 4 months ago by Sanket Shingote ♦♦ 220
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Answer: A: Single ended signaling & differential ended signalling
... i) An important advantage of differential signalling over single ended signalling is higher immunity to environmental noise. ii) Consider fig:(a) Clock line- carries a large clock signal. Signal line- carries small sensitive signal. Due to capacitive coupling between two ...
written 4 months ago by dukare030296hemant50 • updated 4 months ago by Sanket Shingote ♦♦ 220
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Answer: A: Explain LC Oscillator
... i) LC ocsillations is biased at a drain current of $I_1$, if the series resistance of $L_P$ is small, the dc level of $V_{out}$ is close to $V_{DD}$. $V_{out}$ is an inverted sinusoid with an average value near $V_{DD}$ because the inductor cannot sustain a large dc drop. ![enter image ...
written 4 months ago by dukare030296hemant50
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Answer: A: Explain Clock feedthrough & charge injection
... **(a) CLock Feed through:** i) A MOS switch couples the clock transitions to the sampling cap through its ($C_{gd}\,\,or\,\,C_{gs}$) overlap capacitance. ii) The effect is caused by the capacitive coupling between the clock input of precharge device and the dynamic output node. ![enter ...
written 4 months ago by dukare030296hemant50
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Answer: A: Describe non-ideal effect of PLL
... **a) PFD/CP Non-linearities** **i)** Several imperfections in the PFD/CP circuit lead to high ripple on the control voltage even when the loop is locked. Therefore, the ripple modulates the VCO frequency producing a $\omega /f$ that is no longer periodic. ![enter image description he ...
written 4 months ago by dukare030296hemant50
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Answer: A: Explain PLL Topology
... i) A PLL consists of a PD ( Phase detector) and a VCO (Voltage controlled Oscillator) in a feedback loop. ii) PD compares phase of $V_{out}$ and $V_{in}$ generating an error that varies the VCO frequency untill the phases are aligned. i.e loop is locked. ![enter image descriptio ...
written 4 months ago by dukare030296hemant50

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