User: jadhavvaibhav498

Reputation:
20
Status:
Trusted
Location:
Last seen:
8 months, 3 weeks ago
Joined:
10 months, 3 weeks ago
Email:
j***************@gmail.com

Academic profile

None
None
None
None

Posts by jadhavvaibhav498

<prev • 135 results • page 1 of 14 • next >
0
votes
1
answer
308
views
1
answers
Answer: A: Implement F= (5, 7, 10, 14, 15) and G= (6, 7, 9, 13, 15) Using PLAs.
... Given: F= (5, 7, 10, 14, 15) & G= (6, 7, 9, 13, 15) **Karnaugh Mapping:** K-Map is used to minimize Boolean function obtained from the given equations F= (5, 7, 10, 14, 15) & G= (6, 7, 9, 13, 15); ![enter image description here][1] **Logic Diagram:** According to logic function obtaine ...
written 8 months ago by jadhavvaibhav49820
0
votes
1
answer
914
views
1
answers
Answer: A: Write Short note on PLA, PAL architecture.
... **PLA** — a Programmable Logic Array (PLA) is a relatively small FPD that contains two levels of logic, an AND-plane and an OR-plane, where both levels are programmable (note: although PLA structures are sometimes embedded into full-custom chips, we refer here only to those PLAs that are provided as ...
written 8 months ago by jadhavvaibhav49820
0
votes
1
answer
261
views
1
answers
Answer: A: Design Magnitude Comparator using PLAs
... In digital system, comparison of two numbers is an arithmetic operation that determines if one number is greater than, equal to, or less than the other number. So comparator is used for this purpose. Magnitude comparator is a combinational circuit that compares two numbers, A and B, and determines ...
written 8 months ago by jadhavvaibhav49820
1
vote
1
answer
889
views
1
answers
Answer: A: Write Short note on CPLD and FPGA architecture.
... **CPLD** — a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks on a single chip. Alternative names (that will not be used in this paper) sometimes adopted for this style of chip are Enhanced PLD (EPLD), Super PAL, Mega PAL, and others. A CPLD comprises multiple circui ...
written 8 months ago by jadhavvaibhav49820
0
votes
1
answer
286
views
1
answers
Answer: A: Write Short note on RAM and SRAM architecture. OR Compare RAM v/s SRAM.
... | DRAM | SRAM | |--------------------------------------------------------------------|--------------------------------------------------------------------| | The Implementation ...
written 8 months ago by jadhavvaibhav49820
0
votes
1
answer
3.1k
views
1
answers
Answer: A: Write Short note on ROM & RAM architecture.
... 1) **Read-only memory, or ROM,** is a form of data storage in computers and other electronic devices that cannot be easily altered or reprogrammed. RAM is referred to as volatile memory and is lost when the power is turned off whereas ROM in non-volatile and the contents are retained even after the ...
written 8 months ago by jadhavvaibhav49820
0
votes
1
answer
780
views
1
answers
Answer: A: VHDL code for Sequence detector (101) using Mealy state machine.
... **VHDL code for Sequence detector (101) using mealy state machine:** library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mealy is Port ( clk : in STD_LOGIC; din : in STD_LOGIC; rst : in STD_LOGIC; dout : out STD_LOGIC); end mealy; architecture Behavioral of mealy is type state is (st0, st1 ...
written 8 months ago by jadhavvaibhav49820
0
votes
1
answer
665
views
1
answers
Answer: A: VHDL code for Sequence detector (101) using Moore state machine.
... **VHDL code for Sequence detector (101) using moore state machine:** library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity moore is Port ( clk : in STD_LOGIC; din : in STD_LOGIC; rst : in STD_LOGIC; dout : out STD_LOGIC); end moore; architecture Behavioral of moore is type state is (st0, st1 ...
written 8 months ago by jadhavvaibhav49820
0
votes
1
answer
420
views
1
answers
Answer: A: Design a VHDL Code for Ring-Counter.
... **VHDL Code for 4 bit Ring Counter:** library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Ring_counter is Port ( CLOCK : in STD_LOGIC; RESET : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (3 downto 0)); end Ring_counter; architecture Behavioral of Ring_counter is sign ...
written 8 months ago by jadhavvaibhav49820
0
votes
1
answer
1.6k
views
1
answers
Answer: A: Design a VHDL Code for T Flip-Flop.
... **VHDL Code for T FlipFlop** library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity T_FF is port( T: in std_logic; Clock: in std_logic; Q: out std_logic); end T_FF; architecture Behavioral of T_FF is signal tmp: std_logic; begin process (Clock) begin if Clock'event and Clock='1' then if ...
written 8 months ago by jadhavvaibhav49820

Latest awards to jadhavvaibhav498

Centurion 10 months ago, created 100 posts.
Rising Star 10 months ago, created 50 posts within first three months of joining.