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852

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Draw CLA carry chain using dynamic CMOS logic

vlsi design updated 3.7 years ago by phenjoisilab • 0

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758

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design decoder circuit for ROM array

vlsi design updated 3.7 years ago by phenjoisilab • 0

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915

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Give read & write stability criterion for 6 T RAM if the pullup transistors are replaced by resistors

vlsi design updated 3.7 years ago by phenjoisilab • 0

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698

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Draw CMOS implementation of D FF

vlsi design updated 3.7 years ago by phenjoisilab • 0

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773

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Draw JK FF using CMOS & explain its working

vlsi design updated 3.7 years ago by phenjoisilab • 0

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752

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Implement following function using CMOS F=AB+AC+AB

vlsi design updated 3.7 years ago by phenjoisilab • 0

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711

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explain concept of Charge Sharing & Charge Lekage

vlsi design updated 3.7 years ago by phenjoisilab • 0

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1.8k

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Explain effect on drain current due to channel length modulation & velocity saturation

vlsi design updated 3.7 years ago by phenjoisilab • 0

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1.7k

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What are the drawbacks of dynamic CMOS logic show the modification in dynamic CMOS logic to overcome its drawback

vlsi design updated 3.7 years ago by phenjoisilab • 0

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962

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Consider CMOS circuit with following parameters $v_{DD}=3.3v,v_{TOn}=0.6v,v_{TO},p=-0.7v,\mu_nC_{ox}=60 \mu A/v^2, \mu_pC_{ox}=20 \mu A/v^2, (W/L)n=8,(W/L)p=12$Calculate noise margins of the circuit

vlsi design updated 3.7 years ago by phenjoisilab • 0