Mumbai University > Electronics and Telecommunication > Sem 4 > Microprocessor and peripherals

Marks: 5M

Year: May 2014

$HOLD --- \overline{RQ_0} / \overline{GT_0}$ 1. In minimum mode, this line carries the HOLD input signal from another master requesting a local bus. 2. The DMA (direct memory access) controller issues the HOLD signal to request for the system bus. 3. In response 8086 completes the current bus cycle and releases the system bus. 4. In maximum mode, it carries the bi-directional $\overline{RQ_0} / \overline{GT_0}$ (Request/ Grant) signal. 5. The external bus master sends an active low pulse to request for the control over the system bus. 6. In response the 8086 completes the current bus cycle, releases the system bus and sends an active low grant pulse on the same line to the external bus controller. 7. 8086 gets back the system bus only after external bus master sends an active low release pulse on the same line.

RESET-

1. It causes the processor to immediately terminate its present activity. The 8284 clock generator provides this signal.
2. This signal must be active high for at least 4 clock cycles.
3. It clears all the flag register, the Instruction Queue, the DS, SS, ES and IP registers and sets the bits of CS register.
4. Hence the reset vector address of 8086 is FFFF0H (as CS = FFFFH and IP = 0000H).

READY-

1. It is an acknowledgement from the addressed memory or I/O that it will complete the data transfer specially meant for slow devices.
2. Microprocessor samples the READY input between T2 and T3 of a M/C cycle.
3. If READY pin is LOW, microprocessor inserts wait states between T2 and T3 until READY becomes HIGH.