Explain the Interrupt structure of 8086 processor?
1 Answer
  1. An interrupt is a special condition that arises during the working of a microprocessor. The microprocessor services it by executing a subroutine called Interrupt Service Routine (ISR).
  2. There are three sources of interrupts for 8086:
  3. Hardware interrupt-

    These interrupts occur as signals on the external pins of the microprocessor. 8086 has two pins to accept hardware interrupts, NMI and INTR.

  4. Software interrupt-

    These interrupts are caused by writing the software interrupt instruction INT n where ‘n’ can be any value from 0 to 255 (00H to FFH). Hence all 256 interrupts can be invoked by software.

  5. Error conditions (Exception or types)-

    8086 is interrupted when some special conditions occur while executing certain instructions in the program. Example: An error in division automatically causes the INT 0 interrupt.

Interrupt Vector Table (IVT):

enter image description here

  1. The interrupt vector (or interrupt pointer) table is the link between an interrupt type code and the procedure that has been designated to service interrupts associated with that code. 8086 supports total 256 types i.e. 00H to FFH.
  2. For each type it has to reserve four bytes i.e. double word. This double word pointer contains the address of the procedure that is to service interrupts of that type.
  3. The higher addressed word of the pointer contains the base address of the segment containing the procedure. This base address of the segment is normally referred as NEW CS.
  4. The lower addressed word contains the procedure’s offset from the beginning of the segment. This offset is normally referred as NEW IP.
  5. Thus NEW CS: NEW IP provides NEW physical address from where user ISR routine will start.
  6. As for each type, four bytes (2 for NEW CS and 2 for NEW IP) are required; therefore interrupt pointer table occupies up to the first 1k bytes (i.e. 256 x 4 = 1024 bytes) of low memory.
  7. The total interrupt vector table is divided into three groups namely,

    A. Dedicated interrupts (INT 0…..INT 4)

    B. Reserved interrupts (INT 5…..INT 31)

    C. Available interrupts (INT 32…..INT 225)

A. Dedicated interrupts (INT 0…..INT 4):

  1. INT 0 (Divide Error)-

    • This interrupt occurs whenever there is division error i.e. when the result of a division is too large to be stored. This condition normally occurs when the divisor is very small as compared to the dividend or the divisor is zero.
    • Its ISR address is stored at location 0 x 4 = 00000H in the IVT.
  2. INT 1 (Single Step)-

    • The microprocessor executes this interrupt after every instruction if the TF is set.
    • It puts microprocessor in single stepping mode i.e. the microprocessor pauses after executing every instruction. This is very useful during debugging.
    • Its ISR generally displays contents of all registers. Its ISR address is stored at location 1 x 4 = 00004H in the IVT.
  3. INT 2 (Non mask-able Interrupt)-

    • The microprocessor executes this ISR in response to an interrupt on the NMI (Non mask-able Interrupt) line.
    • Its ISR address is stored at location 2 x 4 = 00008H in the IVT.
  4. INT 3 (Breakpoint Interrupt)-

    • This interrupt is used to cause breakpoints in the program. It is caused by writing the instruction INT 03H or simply INT.
    • It is useful in debugging large programs where single stepping is efficient.
    • Its ISR is used to display the contents of all registers on the screen. Its ISR address is stored at location 3 x 4 = 0000CH in the IVT.
  5. INT 4 (Overflow Interrupt)-

    • This interrupt occurs if the overflow flag is set and the microprocessor executes the INTO (Interrupt on Overflow) instruction.
    • It is used to detect overflow error in signed arithmetic operations.
    • Its ISR address is stored at location 4 x 4 = 00010H in the IVT.

B. Reserved interrupts (INT 5…..INT 31):

  1. These levels are reserved by Intel to be used in higher processors like 80386, Pentium etc. They are not available to the user.

C. Available interrupts (INT 32…..INT 225):

  1. These are user defined, software interrupts.
  2. ISRs for these interrupts are written by the users to service various user defined conditions.
  3. These interrupts are invoked by writing the instruction INT n. Its ISR address is obtained by the microprocessor from location n x 4 in the IVT.

Hardware Interrupts:

  1. NMI (Non mask-able interrupt)-

    • This is a non-mask-able, edge triggered, high priority interrupt.
    • On receiving an interrupt on NMI line, the microprocessor executes INT
    • Microprocessor obtains the ISR address from location 2 x 4 = 00008H from the IVT.
    • It reads 4 locations starting from this address to get the values for IP and CS to execute the ISR.
  2. INTR-

    • This is a mask-able, level triggered, low priority interrupt.
    • On receiving an interrupt on INTR line, the microprocessor executes 2 $\overline{INTA}$ pulses.
    • 1st $\overline{INTA}$ pulse – The interrupting device calculates (prepares to send) the vector number.

      2nd $\overline{INTA}$ pulse – The interrupting device sends the vector number ‘N’ to the microprocessor.

    • Now microprocessor multiplies N x 4 and goes to the corresponding location in the IVT to obtain the ISR address. INTR is a mask-able interrupt.
    • It is masked by making IF = 0 by software through CLI instruction.
    • It is unmasked by making IF = 1 by software through STI instruction.
Please log in to add an answer.