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Minimum mode | Maximum mode |
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In minimum mode there can be only one processor i.e. 8086. | In maximum mode there can be multiple processors with 8086, like 8087 and 8089. |

$MN/ \overline{MX}$ is 1 to indicate minimum mode. | $MN/ \overline{MX}$is 0 to indicate maximum mode. |

ALE for the latch is given by 8086 as it is the only processor in the circuit. | ALE for the latch is given by 8288 bus controller as there can be multiple processors in the circuit. |

$\overline{DEN}$and $DT/ \overline{R}$ for the trans-receivers are given by 8086 itself. | and$DT/ \overline{R}$ for the trans-receivers are given by 8288 bus controller. |

Direct control signals $M/ \overline{IO}$, $ \overline{RD}$ and $\overline{WR}$ are given by 8086. | Instead of control signals, each processor generates status signals called $\overline{S_2}$, $\overline{S_1}$ and $\overline{S_0}$. |

Control signals $M/ \overline{IO}$, $ \overline{RD}$ and $\overline{WR}$ are decoded by a 3:8 decoder like 74138. | Status signals $\overline{S_2}$, $\overline{S_1}$ and $\overline{S_0}$ are decoded by a bus controller like 8288 to produce control signals. |

$\overline{INTA}$ is given by 8086 in response to an interrupt on INTR line. | $\overline{INTA}$ is given by 8288 bus controller in response to an interrupt on INTR line. |

HOLD and HLDA signals are used for bus request with a DMA controller like 8237. | $\overline{RQ} / \overline{GT}$,lines are used for bus requests by other processors like 8087 or 8089. |

The circuit is simpler. | The circuit is more complex. |

Multiprocessing cannot be performed hence performance is lower. | As multiprocessing can be performed, it can give very high performance. |

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