Mumbai University > Computer Engineering > Sem 5 > Microprocessor

Marks: 5M

Year: Dec 2015

1. In the maximum mode of operation of 8086, more than one processor is present in the system. i.e. another processor is interfaced with 8086. The other processor may be either a numeric coprocessor 8087 or any other independent processor like 8086 or 8088. All the resources like memory, address bus, data buses are shared between the two processors.
2. The block diagram of the maximum mode configuration system of 8086 is shown in Figure below. In maximum mode three 8-bit latches (IC 8282), two 8-bit transceivers (IC 8286) and one clock generator (8284) are used along with the bus controller 8288.
3. The latches arc used to de-multiplex the multiplexed address/data lines and also address/ status signals. The two transceivers are used to enable the data flow and direction of the data flow. The clock generator is used to generate the clock and also synchronize the READY and RESET signals.
4. The control signals for maximum mode of operation arc generated by the Bus Controller chip 8288. The three status outputsS_0,S_1, S_2 from the processor are input to 8288. The outputs of the bus controller are the Control Signals, namely DEN, DT/R, IORC, IOWTC, MWTC, MRDC, ALE etc. These control signals perform the same task as the minimum mode operation. However, the DEN is an active HIGH signal which has to be convened to active LOW by means of an inverter.