Pentium uses a 5 stage pipeline with the following stages in the pipeline.

1. Prefetch stage - Pentium instructions are variable length and are stored in a prefetch buffer. There is a 256 bit path from instruction cache to the prefetch buffer.

2. Decode 1 stage - In this stage the processor decodes the instruction and finds the opcode and addressing information, check which instructions can be paired for simultaneous execution and participates in branch address prediction.

3. Decode 2 stage - Addresses for memory reference are found in this stage.

1. Execute stage - In this stage, data cache fetch or ALU or FPU operation may be carried out. Observe that two operations can be carried out.

2. Write back stage - Registers and flags are updated based on results of execution.