Mumbai University > Computer Engineering > Sem 5 > Microprocessor

Marks: 10M

Year: May 2015, Dec 2015, May 2016

1. SPARC stands for Scalable Processor Architecture
2. SPARC was designed as a target for optimizing compilers and easily pipelined hardware implementations. SPARC implementations provide exceptionally high execution rates (MIPS) and short time-to-market development schedules.
3. Provide the scalability of the cost/performance ratio of successive implementations with the current improvements in circuit technology.
4. The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from processors required in embedded systems to processors used for servers.
5. It is a Load and store architecture. Operations are always done over registers.
6. Uses “register window” concept thus offering a large number of registers.
7. Uses delay slot to optimize branch instruction.
8. Passes arguments using registers and the stack.

1. Integer Unit
2. Contains the general purpose registers and controls the overall operation of the processor.
3. It may contain from 64 to 528 general-purpose 64-bit r registers. They are partitioned into 8 global registers, 8 alternate global registers, plus a circular stack of from 3 to 32 sets of 16 registers each, known as register windows.

4. Executes the integer arithmetic instructions and computes memory addresses for loads and stores. -Maintains the program counters and controls instruction execution for the FPU.

5. Floating Point Unit

6. The FPU has 32-bit (single-precision) floating-point registers, 64-bit (double-precision) floating-point registers, and 128-bit (quad-precision) floating-point registers.
7. Double-precision values occupy an even-odd pair of single-precision registers.
8. Quad-precision values occupy an odd-even number pair of double precision registers.
9. Floating-point load/store instructions are used to move data between the FPU and memory.
10. The memory address is calculated by the IU.

11. Floating-Point operate (FPop) instructions perform the floating-point arithmetic operations and comparisons.

12. Coprocessor Unit

13. The instruction set includes support for a single, implementation-dependent coprocessor. The coprocessor has its own set of registers.
14. Coprocessor load/store instructions are used to move data between the coprocessor registers and memory floating-point instructions mirrors coprocessor instructions.