Sketch a block representation for an n-channel JFET, showing bias voltages, depletion regions, and current directions. Label the device terminals and explain its operation. Explain the effect of increasing levels of negative gate-source voltage. Also sketch a typical drain characteristics for $V_{GS} = 0$ for an n-channel JFET. Explain the shape of the characteristic, identify the regions, and indicate the important current and voltage levels. -

Mumbai University > Computer Engineering > Sem 3 > Electronic Circuits and Communication Fundamentals

Marks: 10 Marks

Year: May 2014

The figure below shows the n-channel JFET, showing bias voltages, depletion region and current directions:

1.When neither any bias is applied to the gate (i.e. when $V_{GS} = 0$) nor any voltage to the drain w.r.t. source (i.e. when $V_{DS} = 0$), the depletion regions around the P-N junctions, are …