Computer Organization and Architecture - Dec 2014
Information Technology (Semester 4)
TOTAL MARKS: 80
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
Solve any four:
1 (a) What are the types of pipeline hazards?(5 marks) 1 (b) Explain in brief memory mapped I/O.(5 marks) 1 (c) Explain in detail cache coherence.(5 marks) 1 (d) Draw flow chart of Booth's algorithm.(5 marks) 1 (e) Define stored program concept and draw Von Neumann's Architecture.(5 marks) 2 (a) Explain in detail different types of addressing modes.(10 marks) 2 (b) Multiply (-2)10 and (-5)10 using Booth's Algorithm.(10 marks) 3 (a) Explain Wilke's Engine (Hard-wired Control Unit) in detail.(10 marks) 3 (b) Explain virtual memory with reference to memory hierarchy, segments and pages.(10 marks) 4 (a) Explain features of RISC and CISC processors.(10 marks) 4 (b) Explain six stage instruction pipeline with suitable diagram.(10 marks) 5 (a) Explain various high speed memories such as interleaved memories and caches.(10 marks) 5 (b) Explain LRU page replacement policy with suitable example.(10 marks) 6 (a) What is Bus Arbitration? Explain any two techniques of Bus Arbitration.(10 marks)
Write a short note (any two):
Nano programming(5 marks) 6 (b)(ii)
DMA (Direct Memory Access)(5 marks) 6 (b)(iii) Plotter(5 marks)