Computer Organization and Architecture - Dec 2013
Information Technology (Semester 4)
TOTAL MARKS: 80
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks. 1(a) Explain different addressing modes with examples.(10 marks) 1(b) Explain PCI bus architecture in details.(10 marks) 2(a) Explain high-order and low-order memory interleaving techniques.(10 marks) 2(b) A two level memory(M1,M2)has the access time tAl=10-9 sec and tA2 =10-4 sec.What must be the hit ratio H in order for the access efficiency to be at least 65% of its maximum possible value?(10 marks) 3(a) Explain Cache-Memory mapping techniques with examples.(10 marks) 3(b) Explain with neat diagram DMA data transfer techniques.(10 marks) 4(a) Explain general organisation of CPU? State function of following CPU register
MAR, MBR, IR, PC, SP(10 marks) 4(b) Define IO-Modules? State difference between programmable and non-programmable devices with suitable examples.(10 marks) 5(a) Explain difference between Microprogrammed and Hardwired control unit organisation with suitable examples.(10 marks) 5(b) Explain Four-Stages CPU instruction pipeline with neat diagram.(10 marks) 6(a) Explain Booth Multiplication Algorithm and implement for following numbers:11 × 5;(10 marks) 6(b) Explain the Flynn's classification for parallel processing system.(10 marks)
Write a short notes (any two)
7(a) TLB(10 marks) 7(a) RISC and CISC(10 marks) 7(b) SPARC processor.(10 marks)