Question: Explain paging hardware with TLB along with protection bits in page table.
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Mumbai University > Computer Engineering > Sem 5 > Operating System

Marks: 10M

Years: May 2016

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modified 3.0 years ago by gravatar for Pooja Joshi Pooja Joshi750 written 3.0 years ago by gravatar for Snehal B Snehal B10
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  • The TLB is a piece of very fast, associative memory, capable of searching many areas of memory simultaneously. This means that many table entries can be searched at the same time for a logical-page entry. This type of memory is very expensive which means that not much of it is used; MMUs usually use TLBs with between 64 and 1024 entries.

  • The TLB fills up with recent searches when a search is not successful, the entries are added. TLBs store only part of a page table's entries, because the memory is expensive and limited.

  • A new page table causes all the entries stored in the TLB to become useless. When a new page table is used for example, on a context switch the TLB entries must be erased to make sure the new process's logical-address space maps to the old process's physical-address space.

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  • Protection

    • With all the paging and replacement that goes on, it might be easy to forget that there needs to be protective barriers thrown up around memory pages.

    • We need to prevent code from straying beyond the boundaries of its pages. Our scheme must embrace the swapping and paging ideas we have developed. Protection in a paged environment mug focus on physical-memory frames. Since every memory reference goes through the page table to reference frames, we can add protection bits for frames and store them in the page table. These bits can give certain properties for frames: read-only or read-write.

    • For further protection, we can add an execute bit. To support paging, we can add a valid-invalid bit, which indicates if the page being accessed is actually in memory. Note that these protection schemes are focused on the page table. Property bits are the easiest way to provide protection.

    • When logical-to-physical translation is taking place, the nature and owner of the request is also analyzed.

  • If the process that issues the address is not the process that owns the page or if the requested operation is something that is not permitted by the access bits, the attempt is ruled illegal and the operating system is notified. The valid-invalid bit is set when paging occurs. If the bit is set to invalid, this means the page has been swapped to virtual memory and a page fault should be triggered.

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written 3.0 years ago by gravatar for Snehal B Snehal B10
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