Question Paper: Integrated Circuits : Question Paper May 2013 - Electronics & Telecomm. (Semester 5) | Mumbai University (MU)
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## Integrated Circuits - May 2013

### Electronics & Telecomm. (Semester 5)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1 (a) Explain capture range, lock range and pull in time with reference to PLL(5 marks) 1 (b) Explain log amplifier(5 marks) 1 (c) List ideal characteristics of op-amp(5 marks) 1 (d) Explain the working of Schmitt trigger(5 marks) 2 (a) Explain with neat diagram the working of IC 555 as monostable multivibrator state and explain any two applications(10 marks) 2 (b) (i) Draw and explain block diagram of CPLD(6 marks) 2 (b) (ii) Give features of XC 9500 family(4 marks) 3 (a) Design a second order KRC band reject filter with f0=50 Hz and bandwidth =6 Hz(10 marks) 3 (b) Explain in detail any two applications of instrumentaion amplifier(10 marks) 4 (a) Write VHDL Code for 4-bit down counter(10 marks) 4 (b) (i) Explain various documentation standard of sequenctial circuit(6 marks) 4 (b) (ii) Explain switch de-bouncing(4 marks) 5 (a) Explain with output derivation the working of inverting and non-inverting adder circuit(10 marks) 5 (b) Draw and explain the functional block diagram of IC XR-2206(10 marks) 6 (a) Draw the block diagram of IC 565 PLL. Explain in detail FSK demodulation using PLL(10 marks) 6 (b) Design a sequence detector to detect a serial input sequence of 1010. use JK Flip-Flops.(10 marks)

### Write short notes on :-

7 (a) Dual slop A/D Converter(5 marks) 7 (b) LM 380 audio amplifier(5 marks) 7 (c) General architecture of FPGA(5 marks) 7 (d) V to I converter using grounded load(5 marks)