Low power features in Cortex M3 architecture.

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What architectural features of Cortex-M3 make it low power device.

Mumbai University > Electronics Engineering > Sem 7 > Embedded System Design

Marks: 10 Marks

Year: Dec 2015, May 2016

1 Answer

Following are the architectural features which makes Cortex-M3 architecture a low power device:

  1. It has sleep mode and deep sleep mode supports, which can work with various system-design methodologies to reduce power consumption during idle period.
  2. Its low gate count and design techniques reduce circuit activities in the processor to allow active power to be reduced.
  3. Since Cortex-M3 has high code density, it has lowered the program size requirement. At the same time, it allows processing tasks to be completed in a short time, so that the processor can return to sleep modes as soon as possible to cut down energy use.
  4. Starting from Cortex-M3 revision 2, a new feature called Wakeup Interrupt Controller (WIC) is available. This feature allows the whole processor core to be powered down, while processor states are retained and the processor can be returned to active state almost immediately when an interrupt takes place.

The following below explains the various modes available in Cortex M3 for power management.

Sleep Modes:

  1. During sleep mode, the system clock can be stopped, but the free-running clock input could still be running to allow the processor to be woken by an interrupt.
  2. The two sleep modes are as follows:

    a. Sleep: Indicated by the SLEEPING signal from the Cortex-M3 processor

    b. Deep sleep: Indicated by the SLEEPDEEP signal from the Cortex-M3 processor

  3. The sleep modes are invoked by Wait-For-Interrupt (WFI) or Wait-For-Event (WFE) instructions.

  4. The events for invoking the sleep modes can be interrupts, a previously triggered interrupt, or an external event signal pulse via the Receive Event (RXEV) signal.

  5. To decide which sleep mode is to be invoked in case of an event can be set by setting the SLEEPDEEP bit field of the Nested Vectored Interrupt Controller (NVIC) control register
  6. The sleep mode operation of the processor depends on chip design. In some cases the clock signals can be stopped to reduce power consumption. The chip can also be designed to shut down part of the chip to further reduce power, or it is also possible that a design can shut down the chip completely. In a case where the chip is shut down completely, the only way to wake the system from sleep is via a system reset.

Sleep-On-Exit Feature:

  1. Processor can be programmed to go back to sleep automatically after the interrupt routine exit. In this way, we can make the core sleep all the time unless an interrupt needs to be served
  2. To use this feature, we need to set the SLEEPONEXIT bit in the System Control register.
  3. If the Sleep-On-Exit feature is enabled, the processor can enter sleep at any exception return to thread level, even if no WFE/WFI instruction is executed.

Wake-up Interrupt Controller:

  1. A new unit called the Wakeup Interrupt Controller (WIC) is available as an optional component. This controller is coupled to the existing NVIC and is used to generate a wakeup request when an interrupt arrives.
  2. By using the technology called State Retention Power Gating (SRPG) and WIC together, most portions of the Cortex-M3 processor can be powered down during deep sleep, leaving a small amount of logic for state retention.
  3. During this power down state, the WIC remains operational and generates a wakeup request to power up and restore the system state when an interrupt arrives. Maximum interrupt latency in such case is around 20-30 clock cycles.
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