MSP430 architecture compared against Cortex-M3 based architecture

Mumbai University > Electronics Engineering > Sem 7 > Embedded System Design

Marks: 10 Marks

Year: May 2016

1 Answer

Comparison of CortexM3 and MSP430 architectures:

  1. RISC Architecture: Cortex M3 architecture provides a 32 bit RISC architecture whereas MSP430 is 16 bit RISC architecture.
  2. Clock:

    a. MSP430 has two internal oscillators, the digitally-controlled oscillator clock (DCOCLK) and the very low frequency oscillator clock (VLOCLK). There can be locations on the board for two other oscillators, a low frequency crystal oscillator (LFXT1CLK) and a high frequency crystal oscillator (XT2CLK). These four oscillator sources can be used to provide an array of clocks for the CPU and the peripherals.

    • The master clock (MCLK) is derived from any of the four oscillators, and it drives the CPU.
    • The sub-main clock (SMCLK) is derived from any of the four oscillators, and it drives peripherals.
    • The auxiliary clock (ACLK) is derived from either VLOCLK or LFXT1CLK, and it drives peripherals.

    b. Cortex M3 processor has three functional clock inputs:

    • FCLK (Free running processor clock): used for sampling interrupts and clocking debug blocks. FCLK ensures that interrupts can be sampled, and sleep events can be traced, while the processor is sleeping.
    • HCLK is the Processor clock.
    • DAPCLK is Debug port Advanced High-performance Bus Access Port (AHB-AP) clock
  3. Instruction set modes:

    a. Cortex M3 is provided with ARM 32 bit instructions, THUMB 16 bit instructions, THUMB-2 instruction. The Thumb-2 instruction set feature requires no state switching between the ARM 32 bit mode and THUMB 16 bit mode. This saves a lot of instruction cycle. Also many data operations can be clubbed in THUMB mode. Thus Cortex M3 supports both 32 bit and 16 bit operation.

    b. MSP430 is provided with a limited number of powerful instructions.

  4. Real time capabilities :

    a. Cortex M3 is not provided with any real time capabilities. They are generally used for microcontroller profiled application

    b. The design of the MSP430 was driven by the need to provide full real-time capability while still exhibiting extremely low power consumption. But to have a true real-time capability, the device must be able to shift from a low-power mode with the CPU off to a fully active mode with the CPU and all other device functions operating nominally in a very short time. This done using the design of system clock.

  5. Low power modes:

    a. The Cortex-M3 processor is suitable for low-power designs because of the low gate count. It has power-saving mode support (SLEEPING and SLEEPDEEP).

    b. MSP430 has six operating modes, each with different power requirements. Three of these modes are important for battery-powered applications:

    • Active mode — CPU and other device functions run all the time
    • Low power mode 3 (LPM3) — the normal mode for most applications during 99% to 99.9% of the time. This mode is also called done mode or sleep mode
    • Low power mode 4 (LPM4) — the mode typically used during storage. This mode is also called off mode
  6. Stack processing capabilities:

    a. The Cortex-M3 contains two stack pointers, Main Stack Pointer (MSP) and Process Stack Pointer (PSP). They are banked so that only one is visible at a time. With the shadowed stack pointer, stack memory of kernel and user processes can be isolated.

    b. The MSP430 is a true stack processor, with most of the seven addressing modes implemented for the stack pointer (SP) as well as the other CPU registers (PC and R4 through R15). The capabilities of the stack include:

    • Free access to all items on the stack — not only to the top of the stack (TOS).
    • Ability to modify subroutine and interrupt return addresses located on the stack.
    • Ability to modify the stored status register of interrupt returns located on the stack
    • No special stack instructions — all of the implemented instructions may be used for the stack and the stack pointer
    • Byte and word capability for the stack.
  7. On –chip debugging:

    a. Cortex M3 supports JTAG or Serial-Wire debug interfaces. CoreSight debugging solution in Cortex M3 allows the processor status or memory contents to be accessed even when the processor is running. It has built-in support for six breakpoints and four watch points.

    b. MSP430 devices include an on-chip debug module called Enhanced Emulation Module (EEM) which allows advanced debug features such as hardware breakpoints, watch points, range breakpoints, among others. The module provides different levels of debug features based on the specific device being used.

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