written 8.1 years ago by | • modified 8.1 years ago |
Mumbai University > Electronics Engineering > Sem 7 > Embedded System Design
Marks: 10 Marks
Year: Dec 2015
written 8.1 years ago by | • modified 8.1 years ago |
Mumbai University > Electronics Engineering > Sem 7 > Embedded System Design
Marks: 10 Marks
Year: Dec 2015
written 8.1 years ago by |
R0–R12: General-Purpose Registers: R0–R12 are 32-bit general-purpose registers for data operations. 16-bit Thumb instructions can only access a subset of these registers (low registers, R0–R7).
R13: Stack Pointers: The Cortex-M3 contains two stack pointers (R13). They are banked so that only one is visible at a time. The two stack pointers are as follows:
The lowest 2 bits of the stack pointers are always 0, which means they are always word aligned.
R14: The Link Register: When a subroutine is called, the return address is stored in the link register.
R15: The Program Counter: The program counter is the current program address. This register can be written to control the program flow.
Special Registers:
The Cortex-M3 processor also has a number of special registers. They are as follows:
The functions of special register are as follows:
xPSR: Provide arithmetic and logic processing flags (zero flag and carry flag), execution status, and current executing interrupt number. The PSRs are subdivided into three status registers:
a. Application Program Status register (APSR)
b. Interrupt Program Status register (IPSR)
c. Execution Program Status register (EPSR)
N: Negative
Z: Zero
C: Carry/borrow
V: Overflow
Q: Sticky saturation flag
ICI/IT: Interrupt-Continuable Instruction (ICI) bits, IF-THEN instruction status bit
T: Thumb state, always 1; trying to clear this bit will cause a fault exception
Exception number: Indicates which exception the processor is handling
2.PRIMASK: Disable all interrupts except the non maskable interrupt (NMI) and hard fault. Default value of this 1 bit register is 0, which means that no masking is set.
3.FAULTMASK: Disable all interrupts except the NMI. Default value of this 1 bit register is 0, which means that no masking is set.
4.BASEPRI: Disable all interrupts of specific priority level or lower priority level. Default value of this 1 byte register is 0.
5.CONTROL: Define privileged status and stack pointer selection. The register has two bits:
$$\text{CONTROL [1] Stack status: 1 = Alternate stack is used} \\ \text{0 = Default stack (MSP) is used} \\ \text{CONTROL [0]: 0 = Privileged in thread mode} \\ \text{1 = User state in thread mode}$$