Digital design using Verilog/VHDL: Advantages and disadvantages

Mumbai University > Electronics Engineering > Sem 7 > Embedded System Design

Marks: 10 Marks

Year: May 2016

1 Answer

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  1. Very High Speed Integrated Circuit HDL or VHDL is a hardware description language use in VLSI design.
  2. VHDL is a technology independent description which enables creation of design targets for a chose technology (like CPLD, FPGA0 using synthesis tools.
  3. VHDL can be used for describing the functionality and behavior of the system (Behavioral representation) or describing the actual gate and register levels of the system.
  4. VHDL supports concurrent, sequential, hierarchical and timing modeling. The concurrent modeling describes the activities happening in parallel, whereas sequential modeling describes structural aspects and timing model models the timing requirements for design.
  5. The basic structure of a VHDL design consists of an entity, architecture and signals.
  6. The entity declaration defines the name of the function being modeled and its interface to the outside world, their direction and type.
  7. The architecture describes the internal structure and behavior of the model. Architecture can define a circuit using individually connected modules or model its behavior using suitable statements.
  8. A signal connects output and inputs of two blocks and must be defined prior to its use.
  9. VHDL function can be stored in a library which can be re-used.
  10. The HDL model once created is loaded in an HDL simulator. The simulator enables the designer to apply the input stimuli to the design and observe if all the functional errors are absent.
  11. The synthesizer tool now generates an optimized technology dependent circuit at gate level. The inputs to the synthesizer are the HDL program, technology library and constraints. The constraints are the area and the speed.
  12. The next phase of implementation is the FPGA implementation, during the placement stage various instances in the netlist are mapped and their relative positions inside the target FPA resources are fixed.  
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