VLSI Design - Dec 2012
Electronics & Telecomm. (Semester 6)
TOTAL MARKS: 80
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks. 1 (a) What do you mean by clock skew and clock jitter?(5 marks) 1 (b) State the need of input output circuit with neat diagram. (5 marks) 1 (c) What are PVT variations and how does PVT affect integrated circuit?(5 marks) 1 (d) Analog circuit design is difficult as compared to digital circuit design. Justify.(5 marks) 2 (a) What is Elmore delay model? What is the effect of interconnect parasitic on delay? How delay can be reduced?(10 marks) 2 (b) Discuss the concept of charge sharing and explain how it affects reliability of integrated circuit.(10 marks) 3 (a) Give and explain single phase clock system and explain drawbacks.(10 marks) 3 (b) Explain Dynamic CMOS logic. Compare it with static CMOS logic. What is the primary drawback of dynamic CMOS logic? Show to modifications in dynamic CMOS logic to overcome its drawback.(10 marks) 4 (a) Show the implementation of four bit carry look ahead along with all the equations.(10 marks) 4 (b) Draw and explain Manchester carry out circuit using carry kill bit.Also draw k-input dynamic Manchester carry chain circuits.(10 marks) 5 (a) Draw schematic for 6T SRAM cell and explain its stability criteria. Also draw and discuss its butterfly curve. (10 marks) 5 (b) Discuss the programming techniques of EEPROM in detail.(10 marks) 6 (a) Draw and explain clock generation and stabilization network. Also explain how this clock is distributed in integrated circuit.(10 marks) 6 (b) Draw and explain MOS based two stage amplifiers. Also discuss how frequency compensation can be achieved.(10 marks)
Write short notes on any four:-
7 (a) DRAM and refresh logic.(5 marks) 7 (b) Switch capacitor circuit.(5 marks) 7 (c) Cross talk in integrated circuits.(5 marks) 7 (d) Interconnect scaling.(5 marks) 7 (e) Metal migration in interconnect.(5 marks)