VLSI Design - May 2012
Electronics & Telecomm. (Semester 6)
TOTAL MARKS: 80
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks. 1 (a) Explain metal migration in interconnect.(5 marks) 1 (b) Explain programming techniques of EEPROM using hot electron and Fowler-Northeim emission.(5 marks) 1 (c) If the width and length of the interconnect is reduced by 30% then the propagation delay of an interconnect will increase or decrease, by how much % ?(5 marks) 1 (d) Draw and explain Manchester carry out circuit using carry kill bit also draw 4-input dynamic Manchester carry chain circuits.(5 marks) 2 (a) What would be the conductor width of power and ground wires to a 50 MHz clock buffer that drives 100pF of on-chip load to satisfy the metal-migration consideration(JAL=0.5mA/μm)? What is the ground bounce with chosen conductor size? The module is 500 μm from both the power and ground pads and the supply voltage is 5 volts. The rise/fall time of clock is 1ns.(Assume sheet resistance of wire = 0.05 Ω/sq).(10 marks) 2 (b) Draw 1T DRAM cell and explain its write, read, hold and refresh operation.(10 marks) 3 (a) Give and explain the drawback with ripple carry adder. Explain 4-bit CLA adder with its carry equations, logical network and writes its verilog description.(10 marks) 3 (b) Explain how ESD (Electro-Static Discharge) effect the MOSFET. Give and explain input protection circuits.(10 marks) 4 (a) Give and explain the maximum and minimum frequency calculation of clock signal which determine the data transfer rate through cascade logic.(10 marks) 4 (b) Draw 4X4 pseudo-nMOS ROM array circuitry having stored following data.0011, 1010,1100, 0101. Also list the no of address pins, data pins and word lines.(10 marks) 5 (a) Explain the need of frequency compensation in CMOS operational amplifier.(10 marks) 5 (b) Give and explain single phase clock system and explain its drawback.(10 marks) 6 (a) Explain various technique of clock generation. Discuss H tree clock distribution.(10 marks) 6 (b) What is cross talk ICs? Explain various methods to reduce it. (10 marks)
Write short notes on any three:-
7 (a) Low power design consideration.(7 marks) 7 (b) Reliability issues in CMOS circuits.(7 marks) 7 (c) Carry save adder.(7 marks) 7 (d) Switch capacitor amplifier.(7 marks)