Mumbai University > Electronics Engineering > Sem 3 > Digital circuits and design

Marks: 10M

Year: May 2016

VHDL code:

Library :IEEE

Use IEEE.STD_LOGIC_1164_ALL ;

Entity full_adder_vdhl_code is

PORT (A: in STD_LOGIC;

B: in STD_LOGIC;

Cin :in STD_LOGIC;

Cout :in STD_LOGIC ;

end full_adder_vdhl_code ;

architectural behavioral of full_adder_vdhl_code is begin

S <= XOR B XOR Cin;

Cout <=(A AND B) OR (Cin AND A) OR (Cin AND B)

End behavioral;