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Mumbai University > Electronics and Telecommunication Engineering > Sem 3 > Digital Electronics

Marks: 10M

Year: May 2016

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i. This is the addition technique that eliminates the problem due to interstage carry delay.

iii. The carry-look ahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger value bits.

iv. The adder with look ahead carry needs additional hardware but the speed of thus adder is independent of the number of bits. Carry look ahead depends on two things:

a. Calculating, for each digit position, whether that position is going to propagate a carry if one comes in from the right.

b. Combining these calculated values to be able to deduce quickly whether, for each group of digits, that group is going to propagate a carry that comes in from the right.

The full adder realization using AND – OR – EXOR is as shown in figure2. i. To reduce the computation time, there are faster ways to add two binary numbers by using carry look ahead adders.

i. They work by creating two signals P and G known to be Carry Propagator and Carry Generator.

iii. The carry propagator is propagated to the next level whereas the carry generator is used to generate the output carry, regardless of input carry. The block diagram of a 4-bit Carry Look ahead Adder is shown here below - iv. The number of gate levels for the carry propagation can be found from the circuit of full adder.

v. The signal from input carry Cin to output carry Cout requires an AND gate and an OR gate, which constitutes two gate levels.

vi. So if there are four full adders in the parallel adder, the output carry C5 would have 2 X 4 = 8 gate levels from C1 to C5. For an n-bit parallel adder, there are 2n gate levels to propagate through.

vii. The corresponding Boolean expressions are given here to construct a carry look ahead adder. In the carry look ahead circuit we need to generate the two signals carry propagator (P) and carry generator (G),

$Pi = Ai ⊕ Bi$

$Gi = Ai • Bi$

The output sum and carry can be expressed as

$Sumi = Pi ⊕Ci$

$Ci+1 = Gi + (Pi • Ci)$

Having these we could design the circuit. We can now write the Boolean function for the carry output of each stage and substitute for each Ci its value from the previous equations:

$C1 = G0 + P0 • C0$

$C2 = G1 + P1 • C1 = G1 + P1 • G0 + P1 • P0 • C0$

$C3 = G2 + P2 • C2 = G2 P2 • G1 + P2 • P1 • G0 + P2 • P1 • P0 • C0$

$C4 = G3 + P3 • C3 = G3 P3 • G2 P3 • P2 • G1 + P3 • P2 • P1 • G0 + P3 • P2 • P1 • P0 • C0$