Implement the following Boolean equation using single 4:1 MUX and few logic gates:

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Implement the following Boolean equation using single 4:1 MUX and few logic gates:

written 7.3 years ago by

ak.amitkhare.ak • 510

modified 2.3 years ago by

pedsangini276 • 4.7k

Mumbai University > Electronics and Telecommunication Engineering > Sem 3 > Digital Electronics

Marks: 10M

Year: May 2016

F (P, Q, R, S) = ∑M (0, 2, 5, 6, 7, 9, 12, 15)

digital electronics

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written 7.3 years ago by

ak.amitkhare.ak • 510

Fig1 shows the implementation of function using 4:1 multiplexer. Here, three of the variables, B and C are applied to the selection lines. C is connected to the S0 and B is connected to S1. The inputs to the multiplexer are derived from the implementation table.

Step1: Implementation table

enter image description here

$D_0= A ̅B ̅+AB = (A⨀ B)$

$D_1= A ̅ B+ AB ̅=A⨁▒B$

$D_2= A ̅B ̅ + A ̅ B = A ̅ ((B ) ̅+ B) = A ̅$

$D_3= A ̅ B+ AB=((A ) ̅+ A)B = B$

Step2: Multiplexer implementation

enter image description here

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