Mumbai University > Electronics and Telecommunication Engineering > Sem 3 > Digital Electronics

Marks: 10M

Year: Dec 2015

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dmux1 is

port(f:instd_logic;

s:in std_logic_vector(2 downto 0);

y:out std_logic_vector(7 downto 0));

end demux1;

architectural behavioral of dmux1 is begin

$y(0)\lt=f when s="000"else'0';$

$y(1)\lt=f when s="001"else'0';$

$y(2)\lt=f when s="010"else'0';$

$y(3)\lt=f when s="011"else'0';$

$y(4)\lt=f when s="100"else'0';$

$y(5)\lt=f when s="101"else'0';$

$y(6)\lt=f when s="110"else'0';$

$y(7)\lt=f when s="111"else'0';$

end behavioral;