Mumbai University > Electronics and Telecommunication Engineering > Sem 3 > Digital Electronics

Marks: 10M

Year: May 2016

Library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity binary_cntr is

port (clk, cnten, up, rst_bar: in std_logic;

q: out std_logic_vector (1 downto 0) );

end binary_cntr;

architecture Behavioral of binary_cntr is

begin

cntr: process (clk)

Variable count_v : unsigned (1 downto 0);

begin

if rising_edge (clk) then

ifrst_bar = …