Mumbai University > Electronics and Telecommunication Engineering > Sem 3 > Digital Electronics

Marks: 10M

Year: May 2016

Library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity binary_cntr is

port (clk, cnten, up, rst_bar: in std_logic;

q: out std_logic_vector (1 downto 0) );

end binary_cntr;

architecture Behavioral of binary_cntr is

begin

cntr: process (clk)

Variable count_v : unsigned (1 downto 0);

begin

if rising_edge (clk) then

ifrst_bar = ‘0’ then

count_v := (others => ‘0’);

elseifcnten = ‘1’ then

case up is when ‘1’ =>count_v := count_v + 1;

when others =>count_v := count_v - 1;

end case;

end if;

end if;

q <= std_logic_vector (counter_v);

end process;

end behavioral;

temp <= "0000";

elseif ( Clock' event and Clock='1') then

if Load='1' then

temp <= Number;

elseif (Load='0' and Direction='0') then

temp <= temp + 1;

elseif (Load='0' and Direction='1') then

temp <= temp - 1;

end if;

end if;

end process;

Output <= temp;

end Behavioral;