Question Paper: VLSI Design : Question Paper Dec 2012 - Electronics & Telecomm. (Semester 6) | Mumbai University (MU)

VLSI Design - Dec 2012

Electronics & Telecomm. (Semester 6)

(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1(a) Write equation and draw the profile for diffusion from constant source and diffusion from instantaneous source. (5 marks) 1(b) Draw VTC of three CMOS inverter circuits (on same Plot) with KR=1, KR<1 and KR>1. (5 marks) 1(c) Draw the profile indicating sub-threshold conduction in MOSFET and show ideal value of sub-threshold slope on it. (5 marks) 1(d) A microprocessor was fabricated in a 0.25μm technology and was able to operate at 1 MHz, consuming 10 watt using a 2.5v power supply.
i. Using fixed voltage scaling, what will the speed and power consumption of the same processor be if scaled to 0.1 μm technology?
ii. If the supply voltage on the 0.1 μm part were scaled to 1.0 v, what will the power consumption and speed be?
(5 marks)
2(a) With device cross section and band diagram, discuss accumulation, depletion and inversion in MOS capacitor. (10 marks) 2(b) Find the depletion layer with Xd the depletion region charge QBO, the threshold voltage with no source to body voltage VTh0 and the body factor Y of a device with the following physical parameters :
TOX=400oA, NA=1.5x1016 cm-3
ND=1018 cm-3
Nss= (density of singly charged positive surface ions)=5 x 1010 cm-2
(10 marks)
3(a) What is the necessity of design rules? Specify lambda based design rules? Draw CMOS inverter for (W/L)p=3(W/L)n with design rules(indicate scale in terms of lambda on layout). (10 marks) 3(b) What is latch-up in CMOS ? How to prevent latch-up in CMOS? (10 marks) 4(a) Calculate noise margin for the CMOS inverter with the following specifications VDD = 5v,VT0,n=1.0 v, VT0,p=-1.2 v, Kn=100 μA/V2, Kp=100 μA/V2. (10 marks) 4(b) Derive an expression for calculation of VOL and VIL for CMOS inverter. (10 marks) 5(a) Design the circuit and draw layout for the function $$ Y={(D+E+A).(B+C)} $$
using CMOS logic. Also find equivalent CMOS inverter Circuit for Simultaneous switching of all inputs assuming that (W/L)p = 15,for all PMOS and (W/L)n =10 for all NMOS transistors.
(10 marks)
5(b) Draw cross section diagrams and their corresponding masks for all important masking steps required for fabrication of CMOS inverter with n-well process. (10 marks) 6(a) Implement a 2:1 multiplexer circuit using CMOS transmission gates. Write a Verilog module for the circuit at switch level of abstraction. Write a test bench to check the functionality of the circuit. (10 marks)

Write short notes on any four.

7(a) Y-chart representation for VLSI design. (5 marks) 7(b) Dry and wet oxidation process. (5 marks) 7(c) Transistor sizing. (5 marks) 7(d) Butting and buried contact. (5 marks) 7(e) Short channel effects. (5 marks) b(b) Implement CMOS 1-bit full adder and write gate level verilog HDL module for it. (10 marks)

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