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Digital Circuits and Design : Question Paper May 2015 - Electronics Engineering (Semester 3) | Mumbai University (MU)

## Digital Circuits and Design - May 2015

### Electronics Engineering (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1 (a) explain the current sinking and sourcing when two standard TTL gates are connected.(5 marks) 1 (b) Explain glitch problem of ripple counter along with waveform.(5 marks) 1 (c) Draw truth table and circuit of JK flip flop using NAND gates.(5 marks) 1 (d) Draw internal block diagram of IC 7490.(5 marks) 2 (a) Design 4 bit ring counter using IC 74194 and draw Its output waveform.(10 marks) 2 (b) Discuss CPLD XC 9500 architecture with neat block diagram. Describe main features.(10 marks) 3 (a) Design MOD 11 synchronous counter using T flip flop.(10 marks) 3 (b) Identify the circuit shown in figure. Write the state table and draw state diagram for the same. (10 marks) 4 (a) Implement 10 bit comparator using IC 7485.(10 marks) 4 (b) Simplify following logic function and realize using NOR gates.
f(w,x,y,z) = πM (1,2,3,7,10,11) + d (0, 15)
f(w,x,y,z) = πM (3,4,5,6,7,10,11,15)
(10 marks)
5 (a) Identify indistinguishable state in following state table and obtain minimized state diagram.

 PS X=0 X=1 NS Output NS Output A B C D E F G A A D A B D B 0 1 0 1 0 0 0 A F E G C D C 0 1 0 0 0 0 0
(10 marks) 5 (b) Draw a circuit diagram of a CMOS inverter. Draw its transfer Characteristics and explain its operation.(10 marks)

### Write short notes on (any three):

6 (a) K-map.(7 marks) 6 (b) Automatic Test Pattern Generation (ATPG).(7 marks) 6 (c) Mealy and Moore sequential machine.(7 marks) 6 (d) SR flip flop.(7 marks)