Subject: Digital System Design

Topic: Introduction to VHDL

Difficulty: High

Design a VHDL Code for Half Adder:

ENTITY half_adder IS --- Half Adder

PORT(a,b:IN BIT; s,c :OUT BIT);

END half_adder;

ARCHITECTURE half_adder_beh OF half_adder IS

BEGIN

s <= a XOR b; -- Implements Sum for Half Adder

c <= a AND b; -- Implements Carry for Half Adder

END half_adder_beh;