Subject: Digital System Design

Topic: Introduction to VHDL

Difficulty: High

Design a VHDL Code for Full Adder:

ENTITY full_adder IS --- Full Adder

PORT(a,b,c: IN BIT ;

sum, carry : OUT BIT);

END full_adder;

ARCHITECTURE full_adder_beh OF full_adder IS

BEGIN

PROCESS(a,b,c) -- Sensitive on all the three bits

VARIABLE temp :BIT;

BEGIN --- DOES the addition in one DELTA time

temp := a XOR b;

sum <= temp XOR c;

carry <= (a AND b) OR (temp AND c);

END PROCESS ;

END full_adder_beh;